CGM.c

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#include "derivative.h"
#include "CGM.h"
/*
 ******************************************************************************
 * Constants
 ******************************************************************************
 */

/*
 ******************************************************************************
 * Globals
 ******************************************************************************
 */

/*
 ******************************************************************************
 * vfnClockOutputEnable
 ******************************************************************************
 */
void vfnClockOutputEnable(CGMCLKOutConfig_t tMyCGMConfig)
{
  
  /* Start by determining if we want to enable or disable */
  if(TRUE == tMyCGMConfig.P.Enable)
  {
    /* Select input and division factor */
    CGM.OCDSSC.B.SELDIV = tMyCGMConfig.P.Divisor;
    CGM.OCDSSC.B.SELCTL = tMyCGMConfig.P.Source;
    
    /* Enable output */
    CGM.OCEN.R = TRUE;
  }
  else
  {
    /* Disable the output */
    CGM.OCEN.R = CLEAR;
  }
  
  return;
}
/*
 ******************************************************************************
 * vfnClockOutputEnable
 ******************************************************************************
 */
uint8_t u8fnClockPLLConfig(uint8_t u8PLLInstance, uint8_t u8IDF, uint8_t u8ODF,
                           uint8_t u8LDF)
{
  uint8_t  u8Status;
  uint16_t u16Counter;
  
  u8Status = CLEAR;
  u16Counter = CLEAR;
  
  
  /* Start by making sure that our instance is valid */
  if(N_OF_PLL_INSTANCES > u8PLLInstance)
  {
    /* Make sure that passed arguments are within limits */
    if((BIT4 > u8IDF) && (BIT2 > u8ODF) && (BIT7 > u8LDF))
    {
      /* Enable Pll progressive switching */
      CGM.FMPLL[u8PLLInstance].CR.B.EN_PLL_SW = TRUE;
      
      /* Final frequency will be (Fosc * LDF) / (IDF * ODF) */
      CGM.FMPLL[u8PLLInstance].CR.B.IDF  = u8IDF;
      CGM.FMPLL[u8PLLInstance].CR.B.ODF  = u8ODF;
      CGM.FMPLL[u8PLLInstance].CR.B.NDIV = u8LDF;
    
      /* We don't know if settings have taken because we dont know if the    */
      /* PLL is on or off at this point. That will depend on some other fn.  */
    }
    else
    {
      u8Status = INVALID_PLL_DIVIDER;
    }
  }
  else
  {
    u8Status = INVALID_PLL_INSTANCE;
  }
  
  return(u8Status);
}
/*
 ******************************************************************************
 * vfnClearPLLFlag
 ******************************************************************************
 */
void vfnClockClearPLLFlag(uint8_t u8PLLInstance)
{
  CGM.FMPLL[u8PLLInstance].CR.B.PLL_FAIL_FLAG = TRUE;
  return;
}
//void vfnClockPLLConfigureMonitoring(uint8_t u8PLLInstance, uint16_t u16UL, 
//                                    uint16_t u16LL)
//{
//  if(PLL_INSTANCE_0 = u8PLLInstance)
//  {
//    CGM.CMU_0_HFREF_A = u16UL;
//  }
//  return;
//}
/*
 ******************************************************************************
 *
 *  End of file.
 *
 ******************************************************************************
 */